Implement inline Verilog/VHDL through Yosys
Website
http://www.clash-lang.orgFunctional simulation in Haskell from existing Verilog/VHDL code
ProjectID
Clash-VerilogVHDL
Acronym
Clash-VerilogVHDL
Additional Info
Not available yet
Enduser Relevance
Not available yet
Contact
https://nlnet.nl/contact/
Endorsements
Not available yet
Disclaimer
Not available yet
Country: Netherlands
NGI Project: NGI Zero Commons Fund
Status: Early research demo
Category: Trustworthy hardware and manufacturing
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