Klusterlab Wireguard

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Implement Wireguard in Verilog on FPGA

ProjectID

KlusterLab-Wireguard

Acronym

KlusterLab-Wireguard

Additional Info

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Enduser Relevance

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Contact

https://nlnet.nl/contact/

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Status: Early research demo

Category: Network infrastructure (including routing, peer-to-peer and virtual private networking)Trustworthy hardware and manufacturing

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